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AI-ranked
2mo ago
TE
Sr.Staff, Design Verification - CPU Cluster / SoC
Tenstorrent
Bengaluru, Karnataka, India (Hybrid)
Design Verification
RISC-V Engineering
SystemVerilog
UVM
6d ago
TE
Sr. Engineer, Performance Infrastructure
Tenstorrent
Austin, Texas, United States (Hybrid)
RISC V
CPU Design
RISC-V
C++
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