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RTL to GDSII Jobs

Browse 89 RTL to GDSII jobs on Inference Jobs.

21-40 of 89 jobs

3wNV

Senior ASIC Power Engineer

NVIDIA

California, United States (On-site)$136k – $264.5k Yearly
ASIC Engineering
Hardware Engineering
2wD-

Micro-Architect / RTL Design - CPU, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$196k – $300k Yearly
ASIC Design
CPU Design
3wNV

ASIC Design Engineer, Clocks

NVIDIA

Shanghai, Shanghai, China (On-site)
ASIC Design
Digital IC Design
2wNV

Principal Digital Design Engineer

NVIDIA

Santa Clara, California, United States (On-site)$232k – $368k Yearly
ASIC Engineer
Digital Design Engineer
1wNV

Senior Technical Program Manager - VLSI

NVIDIA

Santa Clara, California, United States (On-site)$168k – $322k Yearly
Hardware Engineering
Program Management
1wNV

Senior Integration Engineer

NVIDIA

Tel Aviv-Yafo, Tel Aviv District, Israel (On-site)
ASIC Design Engineer
EDA Engineer
1wNV

Physical Design Engineer

NVIDIA

新竹市, Hsinchu City, Taiwan (On-site)
ASIC Design
Hardware Engineering
1wTE

Senior Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100k – $500k Yearly
ASIC Design
Hardware Engineering
1wTE

Staff Engineer, SoC - DFD Design Verification

Tenstorrent

Boston, Massachusetts, United States (Hybrid)$100k – $500k Yearly
ASIC Design Verification
DFT Engineering
1wCE

AI Silicon Physical Design Engineer

Cerebras

California, United States (Remote)$150k – $250k Yearly
ASIC Design
Physical Design Engineering
2wNV

Senior Digital Design Engineer

NVIDIA

Bengaluru, Karnataka, India (On-site)
ASIC Design
Digital Design
3wNV

Senior GPU Floorplan Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Physical Design
Floorplanning
1wNV

ASIC Design Engineer, High Speed IO

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
Digital Design
1wTE

Sr Staff Engineer, SoC RTL Design

Tenstorrent

Toronto, Ontario, Canada (Hybrid)
ASIC Design
Digital Design
1wNV

Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

NVIDIA

Santa Clara, California, United States (Hybrid)$136k – $264.5k Yearly
ASIC Design
ASIC Physical Design
1wNV

ASIC Design Engineer, BOOT, Functional Safety and Power Management

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
ASIC Design
Digital Design
6dGR

DFT Engineer

Graphcore

Bristol, England, United Kingdom (On-site)
ASIC Design
DFT Engineering
3wD-

Digital Design Engineer, Micro-Architect, Principal

d-Matrix

Santa Clara, California, United States (Hybrid)$180k – $300k Yearly
ASIC Design
Digital IC Design
1wTE

SoC - Chiplet Design Lead

Tenstorrent

Toronto, Ontario, Canada (Hybrid)$100k – $500k Yearly
ASIC Design
Chiplet Architecture
6dNV

DFT Verification Engineer

NVIDIA

臺北市, Taipei, Taiwan (On-site)
ASIC Verification
Design Verification

Related searches

Hardware EngineeringASIC DesignRTL DesignSemiconductor EngineeringVLSI DesignDigital DesignDFT EngineeringSoC DesignVLSIASIC Physical Design