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SystemVerilog Salaries in Santa Clara
Explore SystemVerilog salaries in Santa Clara across 8 jobs
Average salary range
$133.3k – $279.9k
Based on 8 jobs · 14% less than the average SystemVerilog salary on Inference Jobs
25th percentile
$100k
Average
$206.6k
75th percentile
$287.5k
SystemVerilog salary by seniority
| Seniority | Avg. salary | Jobs |
|---|---|---|
| Entry Level | $105.3k – $199.3k | 3 |
| Senior | $150.1k – $328.2k | 5 |
SystemVerilog salaries in other locations
Austin
Avg. $112k – $318.1k · 3 jobs
San Francisco
Avg. $270k – $433.3k · 3 jobs
Toronto
Avg. $100k – $500k · 3 jobs
Top paying skills in Santa Clara
Python
Avg. $164.1k – $302.4k · 205 jobs
C++
Avg. $162.5k – $298.6k · 119 jobs
Deep Learning
Avg. $172.2k – $307.8k · 74 jobs
CUDA
Avg. $166.1k – $291.7k · 70 jobs
Linux
Avg. $164.6k – $292.9k · 62 jobs
PyTorch
Avg. $165.4k – $300.4k · 62 jobs
Top paying titles in Santa Clara
Hardware Engineering
Avg. $153.7k – $305.4k · 95 jobs
Software Engineering
Avg. $171.6k – $315.3k · 81 jobs
AI Engineering
Avg. $183.9k – $335.8k · 35 jobs
Electrical Engineering
Avg. $143k – $307.7k · 33 jobs
Infrastructure Engineering
Avg. $192.9k – $338.0k · 30 jobs
DevOps
Avg. $173.5k – $309.1k · 29 jobs
SystemVerilog salary FAQs for Santa Clara
All salary figures are normalized to USD annual equivalents. Averages are based on published jobs with salary data and filtered for statistical outliers.