SystemVerilog Salaries in Austin
Explore SystemVerilog salaries in Austin across 3 jobs
Average salary range
$112k – $318.1k
Based on 3 jobs · 10% less than the average SystemVerilog salary on Inference Jobs
25th percentile
$100k
Average
$215.0k
75th percentile
$382.3k
SystemVerilog salaries in other locations
Santa Clara
Avg. $133.3k – $279.9k · 8 jobs
San Francisco
Avg. $270k – $433.3k · 3 jobs
Toronto
Avg. $100k – $500k · 3 jobs
Top paying skills in Austin
Python
Avg. $127.9k – $387.8k · 17 jobs
RISC-V
Avg. $100k – $500k · 12 jobs
C++
Avg. $118.2k – $353.8k · 9 jobs
Linux
Avg. $129.1k – $411.5k · 8 jobs
Perl
Avg. $118.3k – $308.8k · 7 jobs
CPU Architecture
Avg. $124k – $348.4k · 5 jobs
Top paying titles in Austin
Hardware Engineering
Avg. $119.6k – $390.0k · 16 jobs
ASIC Design
Avg. $109k – $363.6k · 4 jobs
Infrastructure Engineering
Avg. $100k – $500k · 4 jobs
Physical Design
Avg. $100k – $500k · 4 jobs
Semiconductor Engineering
Avg. $139.3k – $308.6k · 4 jobs
Software Engineering
Avg. $100k – $500k · 4 jobs
SystemVerilog salary FAQs for Austin
All salary figures are normalized to USD annual equivalents. Averages are based on published jobs with salary data and filtered for statistical outliers.