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Physical Design Checks Jobs

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2mo agoNV

ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis
Timing Convergence
3mo agoNV

Formal Equivalence Checking Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
VLSI
Hardware Engineering
Verilog
ASIC Design
5d agoTE

Senior Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Engineering
Physical Design
ASIC Design
3mo agoNV

Senior Physical Design Methodology Engineer, Innovus Flows

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Physical Design Engineer
Methodology Engineer
Physical Design
Innovus
4w agoTE

Senior Engineer, Physical Design – EMIR

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design Engineer
Silicon Engineering
Physical Design
EMIR analysis
2mo agoNV

Senior Software R&D Engineer, VLSI Physical Design

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
Physical Design Engineer
VLSI Engineer
VLSI Physical Design
C++
2mo agoNV

Senior SoC Methodology Architect, VLSI Physical Design

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $218.5K Yearly
Physical Design
VLSI Design
SoC Methodology
VLSI Physical Design
3w agoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
2mo agoCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120K – $240K Yearly
Design Verification
Hardware Engineering
SystemVerilog
UVM
4w agoNV

Circuit Design CAD Engineer

NVIDIA

Shanghai, Shanghai, China (On-site)
CAD Engineering
Circuit Design
CAD
Circuit Design
3mo agoOP

Design Verification Engineer

OpenAI

San Francisco, California, United States (On-site)$310K – $380K Yearly
Hardware Engineering
Design Verification
Design Verification
SystemVerilog