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EM/IR Analysis Jobs

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2mo agoNV

Senior Memory Mask Designer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
VLSI Design
Physical Design
IC Layout
CMOS
2mo agoNV

Senior Circuit Design Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $264.5K Yearly
Circuit Design
Hardware Engineering
Circuit Design
Spice Simulations
3mo agoTE

SoC Top-Level Physical Design Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
SoC Engineering
SoC Physical Design
Floorplanning
1mo agoNV

Circuit Design Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $189.8K Yearly
Circuit Design
Hardware Engineering
Standard Cell Design
ROM Design
4w agoCE

3D Physical Design Engineer

Cerebras

Sunnyvale, California, United States (On-site)$150K – $270K Yearly
Physical Design
ASIC Design
ASIC Physical Design
SoC Physical Design
3w agoCE

Compiler Engineer

Cerebras

Sunnyvale, California, United States (On-site)
Compiler Engineering
Compiler Developer
Compilers
C++
4w agoTE

Senior Engineer, Physical Design – EMIR

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design Engineer
Silicon Engineering
Physical Design
EMIR analysis
2mo agoNV

Memory Mask Design Engineer

NVIDIA

Bengaluru, Karnataka, India (Hybrid)
Memory Design
Mask Design
IC Layout
CMOS
2mo agoNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Hardware Engineering
ASIC Design
ASIC Design
Timing Analysis
1mo agoCE

DVT- Technical Lead

Cerebras

Sunnyvale, California, United States (On-site)$175K – $275K Yearly
Electrical Engineering
Hardware Engineering
DVT
Root Cause Analysis
2mo agoNV

Senior Physical Design Engineer

NVIDIA

Westford, Massachusetts, United States (On-site)$136K – $264.5K Yearly
Physical Design
ASIC Design
VLSI Physical Design
Place and Route
1mo agoNV

Signoff Methodology Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
Methodology Engineering
Static Timing Analysis
Prime-Time
Prime-Shield
2mo agoNV

Senior PDK Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $310.5K Yearly
Semiconductor Engineering
Electrical Engineering
PDK
VLSI Design
2mo agoTE

SoC Physical Design Verification Engineer

Tenstorrent

Austin, Texas, United States (Hybrid)$100K – $500K Yearly
Physical Design
Physical Design Verification
SoC Physical Verification
DRC
4w agoFI

Senior Hardware Failure Analysis Engineer

Figure

San Jose, California, United States (On-site)$120K – $250K Yearly
Hardware Engineering
Failure Analysis
Failure Analysis
PCBAs
1mo agoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
PrimeTime