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RISC-V Jobs in Rio Robles, San Jose, California, United States

Browse 14 RISC-V jobs in Rio Robles, San Jose, California, United States on Inference Jobs.

14 jobs

5dTE

RISC-V AI / HPC & Agentic Software Engineering Lead

Tenstorrent

North America (Remote)$100k – $500k Yearly
AI Engineering
Architecture
3wTE

RISC-V CPU Microarchitecture / RTL

Tenstorrent

United States (Remote)$100k – $500k Yearly
CPU
Digital Design
3wTE

Director, RISC-V Software Ecosystem

Tenstorrent

United States + 1 more (Remote)$100k – $500k Yearly
Embedded Software
Engineering Management
5dTE

Sr. Staff Engineer, Automotive System Software

Tenstorrent

United States (Remote)$100k – $500k Yearly
AI Development
Automotive Software
5dTE

Automotive and Robotics SOC Architect

Tenstorrent

North America (Remote)$100k – $500k Yearly
ASIC Design
Automotive Architecture
2wTE

Staff Engineer, Platform Security Systems Software

Tenstorrent

United States (Remote)$100k – $500k Yearly
Embedded Software
Firmware Engineering
5dTE

Startup GTM

Tenstorrent

New York, United States + 2 more (Remote)$100k – $500k Yearly
Account Management
Business Development
2wTE

High-Performance Computing Architect

Tenstorrent

United States (Remote)$100k – $500k Yearly
Architecture
Hardware Architecture
5dTE

CPU Architect, Load-Store

Tenstorrent

United States (Remote)$100k – $500k Yearly
CPU Architecture
Hardware Engineering
2wTE

Chiplet Physical Design Engineer

Tenstorrent

United States (Remote)$100k – $500k Yearly
ASIC Design Engineer
Hardware Engineer
5dTE

Sr Staff Software Engineer, Toolchain/Compiler

Tenstorrent

Worldwide (Remote)$100k – $500k Yearly
Compiler Engineering
Embedded Systems
5dTE

Memory Architect

Tenstorrent

North America + 1 more (Remote)$100k – $500k Yearly
Chip Architecture
Hardware Architecture
5dCE

AI Silicon Physical Design Engineer

Cerebras

California, United States (Remote)$150k – $250k Yearly
ASIC Design
Physical Design Engineering
1dCE

Design Verification Engineer- Tile

Cerebras

United States (Remote)$120k – $240k Yearly
ASIC Verification
Design Verification

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