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Clock Gating Jobs in California, United States

Discover Clock Gating roles in California, United States on Inference Jobs and apply today.

3w agoET

Front-End Power Engineer

Etched

Cupertino, California, United States (On-site)
Hardware
ASIC Design
RTL Design
Verilog
2mo agoNV

ASIC Clocks Verification Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Verification
Hardware Engineering
ASIC
Design Verification
3mo agoNV

Senior Post Silicon Feature Development Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$168K – $310.5K Yearly
Hardware Engineering
Silicon Engineering
System Design
Semiconductor
3w agoET

ASIC Timing Engineer

Etched

Cupertino, California, United States (On-site)
Hardware Engineering
ASIC Design
ASIC Timing
Static Timing Analysis (STA)
3mo agoNV

ASIC Timing Engineer

NVIDIA

Santa Clara, California, United States (On-site)$116K – $218.5K Yearly
ASIC Engineering
Hardware Engineering
Static Timing Analysis
Timing Convergence
1mo agoTE

Staff Design for Test STA Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
DFT Engineering
STA Engineering
Design for Test
Static Timing Analysis
4w agoD-

Analog Design Engineer (L4/L5)

d-Matrix

Santa Clara, California, United States (Hybrid)$155K – $250K Yearly
Analog Design
Integrated Circuit Design
Analog Mixed Signal Design
Cadence
3mo agoNV

Senior ASIC RTL Integration and Netlisting Engineer

NVIDIA

Santa Clara, California, United States (On-site)$136K – $264.5K Yearly
ASIC Design Engineer
Physical Design Engineer
ASIC
RTL Integration
2mo agoNV

ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA

Santa Clara, California, United States (On-site)$100K – $189.8K Yearly
ASIC Engineering
Physical Design
ASIC
RTL
1mo agoNV

Senior Software Engineer, Hardware Tools and Methodology Development

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
Software Engineer
Senior Software Engineer
C++
Verilog
1mo agoNV

Senior Agentic Systems Engineer, Neural Graphics

NVIDIA

Santa Clara, California, United States (On-site)$184K – $287.5K Yearly
Software Engineering
DevOps
Python
C++
2mo agoNV

Senior Timing Methodology Engineer, Custom Circuits

NVIDIA

Santa Clara, California, United States (On-site)$168K – $310.5K Yearly
Hardware Engineering
ASIC Design
ASIC Design
Timing Analysis
1mo agoTE

Static Timing Analysis (STA) Methodology Engineer

Tenstorrent

Santa Clara, California, United States (Hybrid)$100K – $500K Yearly
Physical Design
ASIC Design
Static Timing Analysis (STA)
PrimeTime
3mo agoNV

Formal Equivalence Checking Methodology Engineer

NVIDIA

Santa Clara, California, United States (Hybrid)$136K – $264.5K Yearly
VLSI
Hardware Engineering
Verilog
ASIC Design
3mo agoOP

Camera Firmware Engineer, Consumer Products

OpenAI

San Francisco, California, United States (Hybrid)$325K – $325K Yearly
Firmware Engineering
Embedded Software
Embedded Systems
Firmware Engineering
3mo agoD-

Analog Design Engineer, Staff

d-Matrix

Santa Clara, California, United States (Hybrid)$155K – $250K Yearly
Analog Design
Mixed Signal Design
Analog Mixed-Signal Design
Cadence